1. Field
This disclosure relates generally to flip-flops, and more specifically, to a flip-flop having logic state retention during a power down mode and method therefor.
2. Related Art
Lower power consumption has been gaining importance in integrated circuit data processing systems due to, for example, wide spread use of portable and handheld applications. Most circuits in handheld devices are typically off (e.g., in an idle or deep sleep mode) for a significant portion of time, consuming only leakage power. As transistor leakage currents increase with finer geometry manufacturing processes, it becomes more difficult to meet chip leakage targets using traditional power reduction techniques. Therefore, reducing leakage current is becoming an increasingly important factor in extending battery life.
One method that has been used to reduce leakage current of integrated circuits is to increase the threshold voltage of the transistors in the device. However, simply increasing the threshold voltage of the transistors may result in unwanted consequences such as slowing the operating speed of the device and limiting circuit performance.
Another method that has been used to reduce leakage current is to “power gate”, or cut off power to certain blocks of the integrated circuit that are not needed when the device is in a low power, or sleep, mode. However, in doing so, the state of the circuit block is lost if a means is not provided to retain the state while in “power down” mode. In a state retention flip-flop, a separate latch may be provided to retain the logic state of the flip-flop during power down mode. While in power down mode, only the separate latch receives a power supply voltage while the other circuits are powered down. However, when entering and exiting power down mode, various clock state restrictions may apply to the state retention flip-flop. The clock state restrictions may be difficult to comply with in some applications. Also, when entering or exiting power down mode, the output of some state retention flip-flops may toggle between logic states. Depending on the application, these characteristics may be undesirable.
Therefore, it would be desirable to have a state retention flip-flop that solves the above problems.